Semiconductor device and its manufacturing method

ABSTRACT

A semiconductor device having area array bump electrodes suitable for flip chip packaging is disclosed. A semiconductor chip with wire bonding electrodes arranged along peripheral edges thereof is provided, then gold wire bump electrodes are formed over the wire bonding electrodes, and thereafter a wiring tape substrate is superimposed on the semiconductor chip and is bonded thereto with an adhesive. On a back surface of the wiring tape substrate are formed wiring connections correspondingly to the electrodes. Further, at the time of bonding with use of the adhesive, convex tips of the gold wire bump electrodes formed respectively on the electrodes of the semiconductor chip pierce through the adhesive to connect the gold wire bump electrodes and the connections electrically with each other. On a surface of the wiring tape substrate are formed area array bump electrodes, whose pitch is larger than the pitch of the electrodes formed on the semiconductor chip.

FIELD OF ART

The present invention relates to a semiconductor device and a method ofmanufacturing the same. Particularly, the present invention is concernedwith a technique which can convert a semiconductor chip having wirebonding electrodes on a surface thereof into a semiconductor devicehaving area array bump electrodes capable of being flip chip packaged.

BACKGROUND ART

Recently, in electronic devices with a semiconductor device incorporatedtherein, not only there has been a tendency to high speed, highfunction, and high packaging density, but also efforts have been madefor the reduction of thickness and weight. Particularly, flip chippackaging of a semiconductor chip (semiconductor element) with LSI, etc.incorporated therein is effective for the attainment of high speed andthickness reduction.

Flip chip packaging methods are broadly classified into the followingtwo methods. (1) Gold stud bumps are formed on peripheral electrodes(e.g., aluminum electrodes) of a semiconductor chip by the wire bondingmethod and thereafter the gold stud bumps (gold salient electrodes) arebonded to a mounting substrate through a thermosetting resin such as ACF(Anisotropic Conductive Film) or NCF (Non Conductive Film), or the goldstud bumps and wiring lines (leads) on a mounting substrate areconnected together using solder, followed by sealing with an insulatingresin. (2) There is adopted a WPP (Wafer Process Package) method whereinfilm forming and patterning steps are repeated for a wafer in themanufacture of a semiconductor chip to form a re-wiring layer whichprovides connection between peripheral electrodes on the semiconductorchip and lands for solder electrodes arranged in a lattice shape, andsolder bump electrodes are formed on the lands for solder electrodes.After subsequent division into individual chips, each of the chips isconnected to a substrate through the solder bump electrodes.

The above flip chip packaging methods give rise to the followingproblems. For preventing signal delay caused by an increase of thewiring length, peripheral electrodes on a semiconductor chip arearranged along an area where input/output circuit elements of thesemiconductor chip are formed, so are generally arranged at a smallspacing (pitch) in a narrow area on a main surface of the semiconductorchip. Therefore, in the above method (1) wherein bump electrodes areformed directly on the peripheral electrodes of the semiconductor chip,the pitch of the bump electrodes thus formed is small and it isaccordingly required to use a build-up type packaging substrate which ismore expensive than the ordinary type of packaging substrates.

In the above method (2), by forming a re-wiring layer, it becomespossible to arrange lands for solder electrodes in a lattice shape ofplural rows and columns over a wide main surface of a semiconductorchip, so that the spacing between adjacent solder bump electrodes alsobecomes wider. However, since the manufacturing process is applied,including defective ships in a state of wafer, an increase of costresults, and it is difficult to form a mechanism for relaxing a thermalstress which is induced between the packaging substrate and thesemiconductor chip in the foregoing WPP method.

As the packaging substrate for the semiconductor device there generallyis employed a ceramic substrate or a printed substrate. In thesepackaging substrates, the pitch of electrodes for connection with thesemiconductor device is about 130 to 160 μm, thus making it impossibleto connect them with peripheral electrodes on the semiconductor chipside having a pitch of 80 to 100 μm directly by flip chip bonding.

For the printed substrate, therefore, there usually is adopted abuild-up method capable of forming fine electrodes, as a substitute forthe conventional laminate method.

However, the build-up method is more complicated in the manufacturingprocess than the laminate method and the resulting substrate is 1.7 to 2times more expensive than the substrate obtained by the laminate method.

Therefore, the present inventor has studied changing electrodes on thesemiconductor chip side from peripheral electrodes to area array bumpelectrodes arranged in a lattice shape of plural rows and columns on amain surface of a semiconductor wafer to widen the electrode pitch andthereby permit the use of a printed substrate fabricated by the lessexpensive laminate method. On the basis of this study the presentinventor accomplished the present invention.

In Japanese Unexamined Patent Publication No. 2000-58594 there isdisclosed a semiconductor device having a structure wherein asemiconductor chip is mounted through an adhesive onto a tape as a bumpsubstrate having plural solder balls for substrate packaging and whereingrooves are formed in the tape surface where the solder balls areformed, allowing stress to be dispersed by the grooves.

It is an object of the present invention to provide a semiconductordevice having area array bump electrodes suitable for flip chippackaging and a method of manufacturing the same.

It is another object of the present invention to provide inexpensively asemiconductor device having area array bump electrodes suitable for flipchip packaging.

It is a further object of the present invention to provide asemiconductor device having a stress relaxing structure between bumpelectrodes arranged in a lattice shape and a semiconductor chip, and amethod of manufacturing the same.

The above and other objects and novel features of the present inventionwill become apparent from the following description and the accompanyingdrawings.

DISCLOSURE OF THE INVENTION

Typical modes of the invention disclosed herein will be outlined below.

-   (1) A semiconductor device comprising:

a semiconductor chip, the semiconductor chip having a main surface, aplurality of semiconductor elements formed on the main surface, and aplurality of electrodes;

gold salient electrodes (gold wire bump electrodes) formed respectivelyon the electrodes of the semiconductor chip;

a wiring substrate (wiring tape substrate), the wiring substrate havingan insulating base layer (tape base) provided with a main surface and aback surface, a plurality of wiring lines formed on the main surface ofthe insulating base layer, and through holes formed in the insulatingbase layer; and

a plurality of solder salient electrodes (area array bump electrodes)formed on the main surface of the wiring substrate and connectedrespectively to the plural wiring lines,

wherein the wiring substrate is disposed in such a manner that the backsurface of the insulating base layer is opposed to the main surface ofthe semiconductor chip,

wherein the back surface of the insulating base layer and the mainsurface of the semiconductor chip are bonded with each other through anadhesive (a thermosetting resin),

wherein the gold salient electrodes are connected respectively to thewiring lines of the wiring substrate in the interiors of the throughholes,

wherein the plural solder salient electrodes are arranged in a latticeshape of plural rows and columns at a pitch larger than a minimum pitchof the electrodes of the semiconductor chip, and

wherein the solder salient electrodes are arranged on the main surfaceof the semiconductor chip through the adhesive and the insulating baselayer.

The sum of the thickness of the insulating base layer and the thicknessof the adhesive is in the range of 50 to 100 μm. The thickness of theinsulating base layer is larger than the thickness (below 50 μm) of theadhesive. The plural wiring lines are formed by a copper film and an Snor NI—Au plating film formed on a surface of the copper film. Theelectrodes of the semiconductor chip are arranged along a peripheralportion of the main surface of the semiconductor chip. The electrodes ofthe semiconductor chip are arranged along an area where input/outputcircuit elements are formed. The solder salient electrodes are arrangedin areas deviated from the areas where the gold salient electrodes areformed. The elastic modulus of the gold salient electrodes is higherthan the elastic moduli of the insulating base layer and the adhesive.The insulating base layer is constituted by a flexible film (a polyimideresin).

The semiconductor device constructed as above is manufactured by amethod comprising the steps of:

providing a semiconductor chip, the semiconductor chip having a mainsurface, a plurality of semiconductor elements formed on the mainsurface, and a plurality of electrodes;

providing a wiring substrate, the wiring substrate having an insulatingbase layer provided with a main surface and a back surface, a pluralityof wiring lines formed on the main surface of the insulating base layer,and through holes formed in the insulating base layer;

forming gold salient electrodes respectively on the electrodes of thesemiconductor chip;

disposing the wiring substrate onto the main surface of thesemiconductor chip through an adhesive (a thermosetting resin)interposed between the back surface of the insulating base layer and themain surface of the semiconductor chip;

thereafter, applying pressure to the wiring substrate to bring the goldsalient electrodes and the wiring lines into mutual contact in theinteriors of the through holes, and applying heat to the adhesive to letthe adhesive cure; and

forming a plurality of solder salient electrodes on the main surface ofthe wiring substrate in such a manner that the solder salient electrodesare connected to the plural wiring lines,

wherein the plural solder salient electrodes are arranged in latticeshape of plural rows and columns at a pitch larger than a minimum pitchof the electrodes of the semiconductor chip, and

wherein the solder salient electrodes are arranged on the main surfaceof the semiconductor chip through the adhesive and the insulating baselayer.

According to the above means (1) there accrue the following advantages.

-   (a) The wire bonding electrodes arranged along the peripheral edges    of a semiconductor chip can be made into solder bump electrodes of a    larger pitch than the pitch of the wire bonding electrodes with use    of a wiring substrate, so that electric characteristics can be    improved. Particularly, the inductance which is essential to    high-speed signal processing can be decreased to about 0.1 nH from    that in the wire bonding method which is 1 to 1.5 nH.-   (b) By making the wire bonding electrodes into solder salient    electrodes having a wider pitch than the pitch of the wire bonding    electrodes and larger than the wire bonding electrodes, it is    possible to enhance the connection reliability in packaging the    semiconductor device.-   (c) Since the wiring substrate with solder salient electrodes formed    thereon is of the same size as the semiconductor chip and is    superimposed on the semiconductor chip in registration with the    chip, it is possible to attain the reduction in size of the    semiconductor device.-   (d) The solder salient electrodes are arranged in areas deviated    from the areas where the gold salient electrodes are arranged.    Further, the elastic modulus of the gold salient electrodes is    higher than the elastic moduli of the insulating base layer and the    adhesive. Therefore, the solder salient electrodes are arranged on    the main surface of the semiconductor chip through the insulating    base layer lower in elastic modulus than the gold salient electrodes    and through the adhesive after curing, whereby when the chip is    mounted on a packaging substrate, a thermal stress induced by a    difference in thermal expansion coefficient between the    semiconductor chip and the packaging substrate can be relaxed by    both insulating base layer and adhesive.-   (e) Between the solder salient electrodes arranged on the main    surface of the semiconductor chip and the semiconductor chip there    is formed a layer of 50 to 100 μm or more in thickness by an organic    resin of a low elastic modulus, whereby a thermal stress induced    between the packaging substrate and the semiconductor chip is    relaxed.-   (f) If an attempt is made to form an adhesive layer at a thickness    of 50 μm or more with use of a thermosetting resin such as ACF or    NCF, there arises the problem that the flatness of solder salient    electrodes formed thereon is deteriorated due to partial variations    in thickness which occur in a heat hardening step. However,    according to the present invention, an insulating base layer is    disposed between the solder salient electrodes and the semiconductor    chip while restricting the thickness of the adhesive layer to a    value of not larger than 50 μm, whereby it is possible to so much    increase the thickness between the solder salient electrodes and the    semiconductor chip. As a result, it is possible to prevent the    deterioration in flatness of the solder salient electrodes.-   (g) Since the insulating base layer is formed by a flexible resin    film and its thickness is about 30 to 100 μm, the stress after the    mounting of the semiconductor device onto the packaging substrate is    relaxed and the packaging reliability is enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view showing a semiconductor deviceaccording to one embodiment (first embodiment) of the present invention;

FIG. 2 is a plan view of the semiconductor device of the firstembodiment;

FIG. 3 is a back view of the semiconductor device of the firstembodiment;

FIG. 4 is a schematic plan view of the semiconductor device of the firstembodiment, showing a state of connection between area array bumpelectrodes and electrodes of a semiconductor chip;

FIG. 5 is a schematic plan view of a semiconductor chip used in thesemiconductor device of the first embodiment;

FIG. 6 is a plan view of a wiring tape substrate used in thesemiconductor device of the first embodiment;

FIG. 7 is a schematic sectional view of the wiring tape substrate;

FIG. 8 is a back view of the wiring tape substrate;

FIG. 9 is a schematic sectional view showing a semiconductor chip withgold wire bump electrodes formed on electrodes of the chip in themanufacture of the semiconductor device of the first embodiment;

FIG. 10 is a schematic sectional view showing an adhesive and a wiringtape substrate both stacked on the semiconductor chip in manufacturingthe semiconductor device of the first embodiment;

FIG. 11 is a schematic sectional view showing in what state the wiringtape substrate is bonded onto the semiconductor chip through an adhesivein manufacturing the semiconductor device of the first embodiment;

FIG. 12 is a schematic sectional view showing the wiring tape substratebonded on the semiconductor chip through the adhesive in manufacturingthe semiconductor device of the first embodiment;

FIG. 13 is a sectional view showing a fixed state of area array bumpelectrodes to the wiring tape substrate in manufacturing thesemiconductor device of the first embodiment;

FIG. 14 is a schematic sectional view showing a part of an electronicdevice on which the semiconductor device of the first embodiment ismounted;

FIG. 15 is a schematic sectional view showing a semiconductor deviceaccording to another embodiment (second embodiment) of the presentinvention;

FIG. 16 is a schematic sectional view showing a semiconductor deviceaccording to a further embodiment (third embodiment) of the presentinvention;

FIG. 17 is a schematic sectional view showing a semiconductor deviceaccording to a still further embodiment (fourth embodiment) of thepresent invention;

FIG. 18 is a schematic plan view of a semiconductor device according toa still further embodiment (fifth embodiment) of the present invention,showing a state of connection between area array bump electrodes andelectrodes of a semiconductor chip;

FIG. 19 is a schematic plan view of a semiconductor device according toa modification of the fifth embodiment, showing a state of connectionbetween area array bump electrodes and electrodes of a semiconductorchip;

FIG. 20 is a schematic diagram showing a method of fabricating asemiconductor device using a multi-substrate tape according to a stillfurther embodiment (sixth embodiment) of the present invention;

FIG. 21 is an enlarged schematic diagram showing a state in which asemiconductor chip is mounted onto a wiring tape substrate inmanufacturing the semiconductor device of the sixth embodiment;

FIG. 22 is a schematic diagram showing in what manner solder salientelectrodes are formed by the supply of solder balls in manufacturing thesemiconductor device of the sixth embodiment;

FIG. 23 is a schematic sectional view showing a multi-chip moduleaccording to a still further embodiment (seventh embodiment) of thepresent invention;

FIG. 24 is a schematic diagram showing an array of electrodes on asemiconductor element and an array of wire bonding pads on a multi-chipmodule substrate in the multi-chip module of the seventh embodiment; and

FIG. 25 is a flow chart showing a method of manufacturing the multi-chipmodule of the seventh embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described in detailhereinunder with reference to the accompanying drawings. In all of thedrawings for illustrating the embodiments of the invention, portionshaving the same functions are identified by like reference numerals, andrepeated explanations thereof will be omitted.

(First Embodiment)

FIGS. 1 to 14 are concerned with a semiconductor device according to oneembodiment (first embodiment) of the present invention, of which FIG. 1is a schematic sectional view of the semiconductor device, FIG. 2 is aplan view thereof, FIG. 3 is a back view thereof, and FIG. 4 is aschematic plan view of the semiconductor device, showing a state ofconnection between area array bump electrodes and electrodes of asemiconductor chip.

As shown in FIG. 1, the semiconductor device of this first embodiment,indicated at 1, is of a structure wherein a wiring substrate (wiringtape substrate) 3 is stacked and bonded onto a main surface (uppersurface in FIG. 1) of a semiconductor chip 2 through an adhesive 4, andsolder salient electrodes (area array bump electrodes) 5 are formed onan exposed surface (upper surface in FIG. 1) of the wiring tapesubstrate 3.

In FIG. 1, two area array bump electrodes 5 are shown in an enlarged andschematic manner also for making the structure of the wiring tapesubstrate 3 clear. More specifically, the area array bump electrodes 5are arranged longitudinally and transversely in a lattice shape as shownin FIG. 2. The following description may partially refer to a case wherethe number of area array bump electrodes 5 is two such as a caseassociated with the manufacturing method.

The semiconductor chip 2 is obtained by dicing longitudinally andtransversely a semiconductor substrate (wafer) of a large diameter whichhas gone through a wafer process. As shown in FIGS. 3 and 5, thesemiconductor chip 2 is formed mainly by a square semiconductorsubstrate (e.g. silicon substrate) 2 a, as shown in FIGS. 3 and 5, withcircuits such as LSI being formed thereon. On a main surface of thesemiconductor substrate 2 a, electrodes (bonding pads) 6 serving ascircuit external terminals are arranged in a row along an area whereinput/output circuits (not shown) are formed (see FIG. 5).

In this first embodiment, the electrodes 6 are arranged, for example,along the peripheral edge of the semiconductor substrate 2 a(semiconductor chip 2), and thus a so-called peripheral electrode arrayis formed. The main surface of the semiconductor substrate 2 exclusiveof this electrode portion is covered with an insulating film(passivation film) 7 (see FIG. 1). The electrodes (bonding pads) 6 areterminals to which wires are connected, and are formed by a thinaluminum or aluminum alloy film. The electrodes 6 are square in shapehaving a size of about 60 to 90 μm, and a minimum pitch “a” thereof (seeFIG. 5) is about 70 to 100 μm. As shown in FIG. 3, a back surface of thesemiconductor chip 2 is a flat silicon face. This silicon face alsoserves as an outer wall face of the semiconductor device 1.

The wiring tape substrate 3 has such a structure as shown in FIGS. 6 to8, of which FIG. 6 is a plan view of the wiring tape substrate, FIG. 7is a schematic sectional view thereof, and FIG. 8 is a back viewthereof.

In this first embodiment, as shown in FIG. 7, the wiring tape substrate(wiring substrate) 3 is superimposed on the semiconductor chip 2 inregistration with the chip and therefore has the same square shape ofthe same size as the semiconductor chip 2. The wiring tape substrate 3comprises an insulating base layer (tape base) 10 formed of an organicresin material and having the same square shape as the semiconductorchip 2, wiring lines 11 formed on a surface of the tape base 10, and aninsulating film (solder resist) 12 (the hatched area in FIG. 6) whichnot only covers the surface of the tape base 10 but also covers thewiring lines 11 selectively.

The areas where the solder resist 12 is not formed, i.e., apertures 13,are for example such circular areas as shown in FIG. 6, to whichconnections as portions of the wiring lines 11 are exposed. In theconnections are formed solder salient electrodes (area array bumpelectrodes) 5 which will be described later. As shown in FIG. 6, theapertures 13 are formed longitudinally and transversely in a latticeshape. The pitch of the apertures, i.e., the pitch “b” of the area arraybump electrodes, is larger than the pitch “a” of the electrodes 6 of thesemiconductor chip 2 shown in FIG. 5. For example, the pitch “a” isabout 80 to 100 μm and the pitch “b” is about 150 to 500 μm. By thusmaking the pitch of the electrodes 6 of the semiconductor chip 2 largerthan the pitch of the area array bump electrodes 5, there can beattained a flip chip packaging superior in packaging performance.

As shown in FIG. 8, through holes (slots) 14 are formed in a backsurface of the tape base 10 along the edges (sides) of the tape base.The slots 14 correspond to the electrodes 6 of the semiconductor chip 2so that the electrodes 6 are positioned within the slots 14 respectivelycorrespondingly when the wiring tape substrate 3 is superimposed on thesemiconductor chip 2.

Outer end portions of the wiring lines 11 formed on the surface of thetape base 10 extent across the slots 14 and form exposed connections.When the wiring tape substrate 3 is superimposed on the semiconductorchip 2, the connections of the wiring lines 11 exposed to the slots 14confront the electrodes 6 respectively of the semiconductor chip 2.

In FIG. 8, the outer end connections of the wiring lines 11 are shown ina rectangular shape schematically. Further, as shown schematically inFIG. 4, predetermined electrodes 6 and predetermined area array bumpelectrodes 5 are eventually connected electrically with each otherthrough predetermined wiring lines 11. FIG. 4 is a schematic plan viewof the semiconductor device, showing a state of connection between theelectrodes 6 of the semiconductor chip 2 and the area array bumpelectrodes 5.

The positions of the apertures 13 are selected so that the area arraybump electrodes 5 are formed at positions deviated from above theelectrodes 6 of the semiconductor chip 2. This is because the area arraybump electrodes are arranged on the main surface of the semiconductorchip 2 through the tape base 10 and the adhesive 4 after curing whichare both lower in elastic modulus than gold wire bump electrodes, sowhen mounted on a packaging substrate 30, a thermal stress induced by adifference in thermal expansion coefficient between the semiconductorchip 2 and the packaging substrate 30 can be relaxed by both tape base10 and adhesive 4. The electrodes 6 are connected to the connections ofthe wiring lines 11 through gold wire bump electrodes although thispoint will be described later.

As shown in FIG. 7, plating films 15 and 16 are formed on surfaces ofthe connections of the wiring lines 11 exposed to bottoms of the slots14 and also on surfaces of the connections of the wiring lines 11exposed to bottoms of the apertures 13.

The tape base 10 is formed by a flexible resin film using, for example,epoxy resin, aramid resin, or polyimide resin. The thickness of the tapebase 10 is preferably about 30 to 100 μm from the standpoint of stressrelaxation after mounting of the semiconductor device 1 onto thepackaging substrate. The wiring lines 11 are formed by etching copperfoil stuck on the tape base into predetermined patterns which copperfoil is usually employed as a wiring material. The wiring portions ofthe wiring lines 11 exposed to the slots 14 and apertures 13 are used aselectrodes, but for decreasing the contact resistance of metal and forpromoting the reactivity of solder it is preferable that those electrodeportions be coated with, for example, nickel or gold, and such platingfilms 15 and 16 as referred to above are formed thereon. For example,the plating films 15 and 16 are Sn plating films or Ni—Au plating films.

The thickness of the tape base 10 is larger than the thickness of thesolder resist 12 so as not to cause warping even upon cure shrinkage ofthe solder resist. For example, when the thickness of the tape base 10is about 20 to 100 μm, that of the solder resist 12 is about 20 to 50μm.

Gold wire bump electrodes 20 are fixed onto the electrodes 6 of thesemiconductor chip 2 and their tips are connected to the plating films15 of the connections of the wiring lines 11. Further, area array bumpelectrodes 5 are fixed respectively to the apertures 13 of the wiringtape substrate 3.

Next, with reference to FIGS. 9 to 13, a description will now be givenabout the manufacture of the semiconductor device 1 of this firstembodiment. As shown in FIG. 9, gold wire bump electrodes 20 are formedon the electrodes 6 of the semiconductor chip 1. Though not speciallyshown, tips of gold wires (for example, 20 to 30 μm in diameter) held bya bonding tool in a conventional wire bonding apparatus are melted witha discharge torch or the like to form balls (for example, 50 to 80 μm indiameter), which are then crushed and fixed onto the electrodes 6 of thesemiconductor chip 2 with the bonding tool. Thereafter, the wires arepulled to cut them at the bonded portions to form such gold wire bumpelectrodes (gold stud bumps) 20 as shown in FIG. 9. Since the cutting ofthe wires is done by pulling the wires, the tip diameter of each goldwire bump electrode 20 becomes smaller than the diameter of each goldwire. The diameter of the ball-like portion fixed to each electrode 6becomes 60 to 90 μm or so and the height thereof becomes 70 μm or so. Inthis first embodiment, as will be described later, pointed portions(convex portions) are utilized for connection to the connections of thewiring lines 11.

Then, as shown in FIG. 10, a semi-solid adhesive 4 and a wiring tapesubstrate 3 both of approximately the same size as the semiconductorchip 2 are superimposed on the surface of the semiconductor chip 2 withthe gold wire bump electrodes 20 formed thereon. In FIG. 10, thesemiconductor chip 2, the adhesive 4, and the wiring tape substrate 3,which are mutually superimposed, are shown separately so as to make iteasier to see.

Next, as shown in FIG. 11, the semiconductor chip 2, the adhesive 4, andthe wiring tape substrate 3 are positioned and sandwiched in between alower mold 25 and an upper mold 26 of a heating/pressing apparatus andare heated and pressed at predetermined temperature and pressure toelectrically connect the gold wire bump electrodes 20 and theconnections of wiring lines 11 exposed to the bottoms of slots 14 formedin the wiring tape substrate 3 with each other. At the same time, theadhesive 4 is heat-cured to fix the wiring tape substrate 3 to thesemiconductor chip 2 (see FIG. 12).

As the adhesive 4 there is used an insulating, thermosetting resin forexample. In this bonding work, the convex portions at the tips of thegold wire bump electrodes 20 formed respectively on the electrodes 6 ofthe semiconductor chip 2 are allowed to pierce through the adhesive 4,thereby connecting the gold wire bump electrodes 20 electrically withthe connections of the wiring lines 11 on the wiring tape substrate 3.Sn or Ni—Au plating film is formed on the surfaces of the connections ofthe wiring lines 11 exposed to the bottoms of slots 14 formed in thewiring tape substrate 3. Thus the bonding between the gold wire bumpelectrodes 20 and the connections is Au—Sn bonding (Au—Sn alloy) orAu—Au bonding.

As the adhesive 4 there also may be used a commercially available NCF(Non Conductive Film) or ACF (Anisotropic Conductive Film). In case ofusing ACF, the gold wire bump electrodes 20 and the connections of thewiring lines 11 exposed to the bottoms of the slots 14 formed in thewiring tape substrate 3 are electrically connected with each otherthrough conductive particles contained in ACF.

Next, as shown in FIG. 13, area array bump electrodes 5 are fixed ontothe connections of the wiring lines 11 exposed to the bottoms ofapertures 13 formed in the wiring tape base 3. A plating film 16, whichis Sn or NI—Au plating film, is formed on the surface of each of theaforesaid connections. For forming the area array bump electrodes 5,solder balls formed by Pb—Sn eutectic solder or Pb free solder are fedto the apertures 13 and area array bump electrodes 5 are formed by heatreflow. For example, area array bump electrodes 5 having a diameter of450 μm and a height of 400 μm are formed by the supply of 400 μm dia.solder balls to the apertures 13.

From the standpoint of relaxing a thermal stress induced between apackaging substrate and the semiconductor chip it is preferable that anorganic resin layer of a low elastic modulus be formed to a thickness of50 to 100 μm or more. However, if a layer of the adhesive 4 is to beformed to a thickness of 50 μm or more with use of a thermosetting resinsuch as NCF, there arises the problem that the flatness of the solderbump electrodes 5 is deteriorated due to partial variations in thicknesswhich occur in the heat-curing step.

In a semiconductor device manufactured by adopting such a method as inthis embodiment wherein not only heat but also pressure is applied atthe time of packaging the semiconductor chip, the above problem offlatness deterioration arises more markedly.

According to a countermeasure effective for solving such a problem, atape base 10 is disposed between the solder salient electrodes 5 and thesemiconductor chip 2 while keeping the layer thickness of the adhesive 4to a value of not larger than 50 μm to increase the thickness of theorganic resin layer formed between the solder bump electrodes 5 and thesemiconductor chip 2.

The tape base 10 may be disposed between the solder salient electrodes 5and the semiconductor chip 2 in the following manner. A wiring tapesubstrate 3 having wiring lines on both surfaces of the tape base 10 isprovided, then solder salient electrodes 5 are formed on thesurface-side wiring lines, and the back-surface wiring lines and thesalient bump electrodes 20 of the semiconductor chip 2 are connectedwith each other. However, the wiring tape substrate 3 having wiringlines on both sides of the tape base 10 is very expensive in comparisonwith a wiring tape substrate 3 having wiring lines on only one side ofthe tape base 10.

In case of using the less expensive wiring tape substrate 3 havingwiring lines on only one side of the tape base 10 as in this embodiment,a back surface of the tape base 10 opposite to a main surface thereof onwhich wiring lines are formed is made face to face with thesemiconductor chip, and the gold salient electrodes 20 and the wiringlines are connected together in the interiors of slots (through holes)14 formed in the tape base, whereby the tape base 10 can be disposedbetween the solder bump electrodes 5 and the semiconductor chip 2.

Although in this first embodiment a single semiconductor chip 2 ismounted on the wiring tape substrate 3, an MCM (multi-chip module)structure may also be constituted by changing wiring patterns of thewiring tape substrate so as to mount a larger number of semiconductorchips 2.

The semiconductor device constructed as above is mounted on a packagingsubstrate in a predetermined electronic device as shown in FIG. 14,which is a schematic diagram showing a part of the electronic device. Ona packaging substrate 30 are mounted the semiconductor device 1 of thisfirst embodiment and semiconductor devices of other package structures,i.e., QFP (Quad Flat Package) 31, BGA (Ball Grid Array) 32, and CSP(Chip Size Package) 33. Of course, on the packaging substrate 30 arealso mounted other electronic parts such as resistors, capacitors, andconnectors, though not shown.

The following effects are obtained according to this first embodiment.

-   (1) The semiconductor chip 2 with wire bonding electrodes 6 arranged    along the peripheral edges of the chip, available as a bare chip,    can be made into area array bump electrodes 5 of a larger pitch than    the electrodes 6 by using the wiring tape substrate 3, so that it is    possible to improve electric characteristics. For example, the    inductance which is essential to high-speed signal processing can be    decreased from 1 to 1.5 nH to about 0.1 nH in comparison with CSP    using the wire bonding method. This is because wire bonding is not    used in the present invention and therefore the inductance of 1 to    1.5 nH, which depends on the wire length in wire bonding, is not    included at all.-   (2) By making the wire bonding electrodes 6 into the area array bump    electrodes 5 larger in size and wider in pitch than the electrodes 6    it is possible to enhance the connection reliability at the time of    packaging the semiconductor device 1.-   (3) Since the wiring tape substrate 3 with the area array bump    electrodes 5 formed thereon is of the same size as the semiconductor    chip 2 and is constructed so as to be superimposed on the    semiconductor chip in registration with the chip, it is possible to    reduce the size of the semiconductor device 1.-   (4) The area array bump electrodes 5 are arranged in areas deviated    from the areas where the gold wire bump electrodes 20 are arranged.    Further, the elastic modulus of the gold wire bump electrodes 20 is    higher than the elastic moduli of the tape base 10 and the adhesive    4. Thus, the area array bump electrodes 5 are arranged on the main    surface of the semiconductor chip 2 through the tape base 10 and the    adhesive 4 after curing both lower in elastic modulus than the gold    wire bump electrodes 20, whereby when the semiconductor chip 2 is    mounted on the packaging substrate 30, a thermal stress induced by a    difference in thermal expansion coefficient between the    semiconductor chip and the packaging substrate can be relaxed by    both tape base 10 and adhesive 4.-   (5) Between the semiconductor chip 2 and the area array bump    electrodes 5 disposed on the main surface of the chip there is    formed an organic resin layer of a low elastic modulus at a    thickness of 50 to 100 μm or more, whereby a thermal stress induced    between the packaging substrate 30 and the semiconductor chip 2 is    relaxed.-   (6) If the layer thickness of the adhesive 4 formed by a    thermosetting resin such as ACF or NCF is to be set at 50 μm or    more, there arises the problem that the flatness of the area array    bump electrodes 5 formed thereon is deteriorated due to partial    variations in thickness which occur in the heat-curing step.    According to the present invention, however, the tape base 10 is    disposed between the area array bump electrodes 5 and the    semiconductor chip 2 while keeping the layer thickness of the    adhesive 4 to below 50 μm, whereby it is possible to ensure a    sufficient thickness of the organic resin layer between the area    array bump electrodes 5 and the semiconductor chip 2 and    consequently it is possible to prevent a lowering in flatness of the    area array bump electrodes 5.-   (7) Since the insulating base layer is formed by a flexible resin    film, i.e., the tape base 10, and its thickness is about 30 to 100    μm, the stress after mounting the semiconductor device 1 onto the    packaging substrate 30 is relaxed and hence the packaging    reliability is improved.-   (8) The reduction in size and weight and speed-up of the    semiconductor device 1 are important factors in the field of    communication devices and the field of portable devices. A higher    function can be achieved by packaging the semiconductor chip 2 in    accordance with a flip chip packaging method and by adopting an MCM    structure. A high-density MCM can be attained by mounting DRAM    (Dynamic Random Access Memory), SRAM (Static Random Access Memory),    flash memory, logic IC, and high-frequency IC onto a single    substrate.    (Second Embodiment)

FIG. 15 is a schematic sectional view showing a semiconductor deviceaccording to another embodiment (second embodiment) of the presentinvention. In the previous first embodiment the electrodes 6 formed onthe main surface of the semiconductor chip 2 are arranged in aperipheral array in which they are arranged along the edges of thesemiconductor chip 2. But according to the construction of this secondembodiment, electrodes 6 are arranged near the center of a semiconductorchip 2 and along an area where a semiconductor element for I/O circuitis disposed (central electrode array), and a wiring tape substrate 3 issuperimposed and stuck through an adhesive 4 onto the semiconductor chip2 with the electrodes 6 thus arranged thereon, further, area array bumpelectrodes 5 are mounted to predetermined positions of the wiring tapesubstrate 3. Also in this construction there can be obtained the sameeffects as in the first embodiment.

Although in this second embodiment the electrodes 6 are arranged in onerow along the center of the semiconductor chip 1, there also may beadopted a combination thereof with a semiconductor chip 2 whereinelectrodes 6 are arranged in two or more plural rows.

(Third Embodiment)

FIG. 16 is a schematic sectional view showing a semiconductor deviceaccording to a further embodiment (third embodiment) of the presentinvention. In this third embodiment, wiring lines in a wiring tapesubstrate 3 are formed in multiple layers to increase the degree ofmargin for wiring distribution.

More specifically, in the semiconductor device 1 of the firstembodiment, one interlayer insulating film 40 of a predetermined patternis formed on the wiring lines 11 formed on the surface of the tape base10, then wiring lines 11 a are formed on the interlayer insulating film40 and are covered with the solder resist 12 which is formedselectively, further, there are formed area array bump electrodes 5connected electrically to the wiring lines 11 a.

The wiring lines 11 connected electrically to the gold wire bumpelectrodes 20 formed on the electrodes 6 of the semiconductor chip 2 andthe area array bump electrodes 5 formed on the surface of the tape base10 are conducted with each other through wiring lines 11 a and 11located respectively above and below the interlayer insulating film 40.

In this third embodiment there may be adopted a construction wherein thenumber of the interlayer insulating film is increased to obtain a largernumber of wiring layers. In this case, wiring lines are formed on eachof the interlayer insulating films and the wiring lines on the top layerof interlayer insulating film are covered with the solder resist whichis formed selectively, further, the bottom layer of wiring linesconnected electrically to the gold wire bump electrodes which are formedon the electrodes of the semiconductor chip and the area array bumpelectrodes formed on the surface of the tape substrate are conductedwith each other through upper and lower wiring lines of the interlayerinsulating film.

If there is adopted a structure wherein at least wiring lines for powersupply and for the ground are provided on the wiring tape substrate onthe side where the semiconductor chip is fixed, it is possible tostabilize the potential and improve electric characteristics. Further,also in this third embodiment, an MCM structure can be obtained byfixing plural semiconductor chips to the wiring tape substrate.

In this third embodiment, by providing plural wiring layers, the areaarray bump electrodes 5 can be arranged in a still higher density andhence it becomes possible to attain a multi-pin structure of asemiconductor device.

For attaining a multi-layer wiring structure there also may be adopted astructure wherein wiring lines are formed on both surface and backrespectively of a single tape base. In this structure, the wiring linesformed on both such surface and back are conducted with each otherthrough through-holes formed in the tape base. The wiring lines on thesurface of the tape base are covered selectively with solder resistprovided on the wiring tape substrate. The portions not covered with thesolder resist serve as apertures for the formation of area array bumpelectrodes.

Also in this example, as is the case with the previous example, if thereis adopted a structure wherein at least wiring lines for power supplyand for the ground are provided on the wiring tape substrate on the sidewhere the semiconductor chip is fixed, it is possible to stabilize thepotential and improve electric characteristics. Further, by fixingplural semiconductor chips to the wiring tape substrate, it is possibleto also attain an MCM structure.

(Fourth Embodiment)

FIG. 17 is a schematic sectional view showing a semiconductor deviceaccording to a still further embodiment (fourth embodiment) of thepresent invention. According to this fourth embodiment, the pitch ofarea array bump electrodes 5 can be made wider.

More specifically, in this fourth embodiment, the wiring tape substrate3 in the semiconductor device of the first embodiment is made larger(larger in area) than the semiconductor chip 2, as shown in FIG. 17.According to the structure of this fourth embodiment, the outerperiphery of the wiring tape substrate 3 is projected from all theperipheral edges of the semiconductor chip 2.

In this embodiment, since the wiring tape substrate 3 can be made wide,the pitch of the area array bump electrodes 5 can be made larger thanthat in the first embodiment and hence it is possible to set large thepitch of electrodes on the packaging substrate for packaging thesemiconductor device of this embodiment.

(Fifth Embodiment)

FIG. 18 is a schematic plan view of a semiconductor device according toa still further embodiment (fifth embodiment) of the present invention,showing a state of connection between area array bump electrodes andelectrodes formed on a semiconductor chip. In the semiconductor deviceof this fifth embodiment, indicated at 1, out of plural solder salientelectrodes (area array bump electrodes) 5 formed on a main surface of awiring substrate (wiring tape substrate) 3, at least one solder salientelectrode 5 is connected to plural electrodes 6 out of plural electrodes6 formed on a main surface of a semiconductor element (semiconductorchip) 2, thus serving as a common electrode.

As shown in FIG. 18, four solder salient electrodes 5 arranged centrallyand dotted for clarity serve as common electrodes. Since some of thesolder salient electrodes 5 thus serve as common electrodes, the numberof the electrodes 5 can be made smaller than that of the electrodes 6 ofthe semiconductor chip 6. The electrodes 6 which are connected throughwiring lines 11 to the solder salient electrodes 5 serving as commonelectrodes are also dotted.

In the semiconductor device of the first embodiment, etc., since wiringlines are formed on only one side of the wiring substrate (wiring tapesubstrate) 3, the wiring freedom is smaller than that in theconventional structure having multi-layer interconnection on a resinsubstrate. In this fifth embodiment, in view of this point, there areformed bump lands connected to plural electrodes 6 on the semiconductorchip 2 and the number of such bump lands is set smaller in comparisonwith the on-chip electrodes 6, thereby ensuring a larger space which iseffective for the distribution of wiring on the wiring tape substrateand permitting connection with a semiconductor chip having a largernumber of pins, even in a single-layer wiring structure. The commonelectrodes (common wiring lines) are used for the supply of ground (GND)potential and source potential.

FIG. 19 is a schematic plan view of a semiconductor device according toa modification of the fifth embodiment, showing a state of connectionbetween area array bump electrodes and electrodes of semiconductorchips. It is effective for the common wiring lines to be used for thesupply of GND potential and source potential. In this case, as shown inFIG. 19, in the electrodes 6 connected to the common solder salientelectrodes 5 through wiring lines 11, if the widths of the wiring lines11 are widened as shown with hatching to adjust the spacing between themand signal I/O wiring lines, it is possible to change wiringcharacteristics such as wiring impedance.

(Sixth Embodiment)

FIGS. 20 to 22 are concerned with a method of manufacturing asemiconductor device according to a still further embodiment (sixthembodiment) of the present invention, of which FIG. 20 is a schematicdiagram showing a semiconductor device manufacturing method using aband-like wiring tape substrate (multi-substrate tape).

The semiconductor device manufacturing method used in this sixthembodiment is a reel-to-reel method. According to this reel-to-reelmethod, as shown in FIG. 20, a band-like wiring tape substrate 3(multi-substrate tape) having semiconductor device-forming areas atpredetermined intervals is unwound from a reel 45, then an assemblingwork is performed, including mounting of a chip 2 on each of thesemiconductor device-forming areas and formation of solder salientelectrodes 5, and the wiring tape substrate 3 is wound round a take-upreel 46. A reel 48 for cover tape may be used. In this case, a covertape 47 is unwound from the cover tape reel 48 and the wiring tapesubstrate 3 is wound round the take-up reel 46 while sandwiching thesemiconductor chip 2 in between the wiring tape substrate 3 and thecover tape 47, whereby products can be protected.

The structure of the multi-substrate tape (wiring tape substrate) is thesame as that of the wiring substrate (wiring tape substrate) 3 used inthe first embodiment. In the illustrated embodiment, a tape-like NCF isalready affixed as adhesive 4 onto a main surface of the wiring tapesubstrate 3.

In FIG. 20, as assembling work stations, a chip bonding (chip mounting)station A, a ball affixing station B, and a ball reflow station C arearranged in the moving direction of the wiring tape substrate 3(multi-substrate tape).

In the chip mounting station A, a semiconductor chip 2 is held by vacuumsuction at a lower end of a collet 50 and the semiconductor chip 2 isfixed to a predetermined product-forming area on the wiring tapesubstrate 3. FIG. 21 is an enlarged schematic diagram showing in whatstate the semiconductor chip is mounted onto the wiring tape substrate.The semiconductor chip which has been carried by the collet 50 isbrought down and fixed onto the product-forming area on the wiring tapesubstrate 3 in a state in which gold wire bump electrodes 20 stand faceto face with the wiring tape substrate 3.

More specifically, as shown in FIG. 21, a thermosetting adhesive 4constituted by NCF is affixed to an upper surface of the wiring tapesubstrate 3 on the stage 51. With descent of the collet 50, the goldwire bump electrodes 20 formed on a lower surface of the semiconductorchip 2 get into through holes (slots) 14 formed in the wiring tapesubstrate 3. At this time, tips of the gold wire bump electrodes 20break through the adhesive 4 and come into contact with plating films 15positioned at the bottoms of the slots 14. By pressing of the collet 50against the stage 51 and by heating from the stage 51, etc. the goldwire bump electrodes 20 is connected to the wiring lines 11 through theplating films 15.

With the above heat and pressure, the adhesive 4 cures and therebyensures positive bonding of the semiconductor chip 2 to the wiring tapesubstrate 3.

The connections of the wiring lines 11 exposed to the bottoms of theslots 14 formed in the wiring tape substrate 3 are each coated on thesurface thereof with Sn or NI—Au plating film, so that the bondingbetween the gold wire bump electrodes 20 and the connections is Au—Sn(Au—Sn alloy) or Au—Au bonding. As is the case with the firstembodiment, ACF is also employable as the adhesive 4.

In the ball affixing station B, plural metallic balls 56 are held in amatrix shape on a flat main surface of a ball supply jig 55. Though notshown, this holding operation is performed by vacuum suction throughvacuum suction holes formed in the main surface of the ball supply jig55. The vacuum suction holes are formed correspondingly to apertures 13formed in the wiring tape substrate 3.

FIG. 22 is a schematic diagram illustrating a state of operation of theball supply jig 55 which holds solder balls as metallic balls 56 byvacuum suction and supplies the solder balls to the wiring tapesubstrate 3. As shown in FIG. 22, the ball supply jig 55, with its mainsurface facing down, moves to the position above a ball supply box 57which accommodates the metallic balls 56 and then moves down to apredetermined height. In this state, vacuum suction is performed to letthe metallic balls 56 be held in the vacuum suction holes.

Next, the ball supply jig 55 rises, then moves leftwards, again movesdown to a predetermined height, allowing the metallic balls 56 held bythe ball supply jig 55 to be dipped into a flux solution 59 contained ina flux vessel 58 and coated with the flux solution.

Next, the ball supply jig 55 again rises to a predetermined height, thenmoves leftwards and stops just under the wiring tape substrate 3(multi-substrate tape) which is at a standstill in the ball affixingstation B. Thereafter, the ball supply jig 55 turns over 180° around ashaft 60 so that its main surface faces up. Next, the ball supply jig 55rise to a predetermined height and supplies the metallic balls 56 heldon its main surface to a lower surface of the wiring tape substrate 3.By utilizing the bonding force of the flux solution, the metallic balls56 are bonded onto plating films 16 formed on the bottoms of theapertures 13 which are formed in the lower surface of the wiring tapesubstrate 3. Thereafter, vacuum suction is stopped and the ball supplyjig 55 is moved down to a predetermined height.

In the next ball reflow station C, the metallic balls 56 thus bonded tothe lower surface of the wiring tape substrate 3 are temporarily heated(reflowed) by means of upper and lower heaters 61. With this reflow, themetallic balls 56 soften and melt, whereby solder salient electrodes(area array bump electrodes) 5 are formed on surfaces of the wiringlines 11 with plating films 16 formed thereon.

The wiring tape substrate 3 with the semiconductor chip 2 mounted andthe solder salient electrodes 5 formed thereon is then wound round thetake-up reel 46 intermittently together with the cover tape 47. Theresulting product is shipped in the state of the take-up reel 46, thenon the user side the wiring tape substrate 3 is cut off and thesemiconductor device 1 is removed.

As described above, in accordance with the reel-to-reel method there ismade electric connection between the semiconductor chip and the wiringtape substrate, and in case of sealing the semiconductor chip with resinfor protecting the main surface of the chip, there is used NCF. Thus, itis desirable to adopt means which uses a thermocompression-bonding jigthrough a thermosetting resin to mount the semiconductor chip onto thewiring tape substrate.

As means for mounting the semiconductor chip onto the wiring tapesubstrate there are known, for example, means wherein transfer moldingis performed after wire bonding and means wherein there is made sealingwith an under-fill resin after solder bump reflow packaging. However, nomatter which means may be adopted, there arises the problem that it isdifficult to take matching with another process which uses thereel-to-reel method.

In contrast therewith, the means which performstheremocompression-bonding with use of a thermosetting resin isadvantageous in that not only it is easy to take matching with respectto, for example, process time in ball affixing and ball reflow processand assembling and construction, but also it is possible to prevent theoccurrence of a connection defect.

(Seventh Embodiment)

FIGS. 23 to 25 are concerned with a semiconductor module (multi-chipmodule) according to a still further embodiment (seventh embodiment) ofthe present invention. As shown in FIG. 23 which is a schematicsectional view, the semiconductor module of this embodiment, indicatedat 70, has an insulating module substrate 71. The module substrate 71has plural connecting electrodes 72 on a main surface thereof and hasplural external electrode terminals 73 on a back surface (lower surfacein the figure) thereof. Though not shown, predetermined externalelectrode terminals 73 and predetermined connecting electrodes 72 areelectrically connected with each other through conductors which extendthrough the interior of the module substrate 71. Each of the externalelectrode terminals 73 comprises a wiring line 73 a formed on the backsurface of the module substrate 71 and a bump electrode 73 b formed onthe wiring line 73 a, and is thus BGA type.

The connecting electrodes 72 on the main surface of the module substrate71 are arranged in a matrix shape (area array shape) correspondingly tothe array of solder bump electrodes 5 on the semiconductor device 1 ofthe first embodiment so as to permit mounting thereon of thesemiconductor device. Such a group of connecting electrodes 72 areprovided in various portions of the module substrate 71 as necessary.

Outside a certain group of connecting electrodes 72, in other words,outside the matrix-arrayed connecting electrodes, there are providedconnecting electrodes 72 a in the form of a frame which electrodes 72 aserve as wire bonding pads. In FIG. 23, the connecting electrodes 72 aare arranged on the left-hand side.

The solder salient electrodes 5 on the semiconductor device 1 are fixed(face-down fixed) to the connecting electrodes 72 by reflow and thesemiconductor device 1 is mounted on the module substrate 71. Further, asemiconductor element (semiconductor chip) 75 is fixed onto theleft-hand semiconductor device 1 through an adhesive (not shown). Asshown in FIG. 24, the semiconductor chip 75 has electrodes 76 on anexposed side thereof. The electrodes 76 and the connecting electrodes 72a on the main surface of the module substrate 71 are connected togetherthrough conductive wires 77.

It is optional whether the adhesive for fixing the semiconductor chip 75is to be a conductive one or a non-conductive one. In case of using aconductive adhesive, if the substrate which constitutes thesemiconductor chip 75 is silicon or a compound semiconductor, thesubstrate becomes equal in potential to the silicon substrate whichconstitutes the semiconductor chip 2 in the semiconductor device 1.Thus, according to the circuit configurations of the semiconductor chips2 and 75, there sometimes is a case where both can be made common toeach other in GND potential.

As shown in FIG. 24, the plural connecting electrodes 72 a to which thewires 77 on the main surface of the module substrate 71 are connectedhave a larger pitch (d) than a minimum pitch (a) of plural electrodes 76formed on the main surface of the semiconductor chip 75, thus providinga re-wiring structure.

As described in the first embodiment, the plural solder salientelectrodes 5 are arranged in a lattice shape comprising plural rows andcolumns at a larger pitch than the minimum pitch of electrodes 6 on thesemiconductor chip 2, thus also providing a re-wiring structure. Thesere-wiring structures make it easier to mount the semiconductor chip.

The following structural characteristics are as described in the firstembodiment. The sum of the thickness of an insulating base layer (tapebase) 10 in the semiconductor device 1 and the thickness of an adhesive4 is 50 to 100 μm, the thickness of the insulating base layer in thesemiconductor device 1 is larger than that of the adhesive 4, and thethickness of the adhesive 4 in the semiconductor device 1 is equal to orless than 50 μm. On a main surface of the insulating base layer of thesemiconductor device 1 is formed an insulating film (solder resist) 12which covers a part of wiring lines 11, and the thickness of theinsulating base layer 10 is larger than the thickness of the insulatingfilm 12. Further, the elastic modulus of gold salient electrodes (goldwire bump electrodes) 20 on the semiconductor device 1 is larger thanthe elastic moduli of the insulating base layer 10 and the adhesive 4.Also in the semiconductor module 70 these structural characteristicsbring about the same effects as in the semiconductor device 1.

On the main surface side of the module substrate 71 there is formed asealing member 79 of an insulating resin by one-side molding inaccordance with transfer molding. The semiconductor device 1,semiconductor chip 75, connecting electrodes 72, 72 a, and wires 77 arecompletely covered with the sealing member 79.

The semiconductor module 70 of this seventh embodiment is fabricated inaccordance with the flow chart of FIG. 25. As shown in the same flowchart, though not illustrated diagrammatically, a semiconductor chip 75is provided (S101), then gold wire bump electrodes 20 are formed onelectrodes of the semiconductor chip (S102), and the semiconductor chip2 is bonded to a wiring tape substrate 3 (S103).

Next, metallic balls (solder balls) are affixed to predeterminedpositions of the wiring tape substrate 3 (S104) and thereafter thesemiconductor device alone is tested (test the semiconductor devicealone: S105).

Then, a module substrate 71 is provided, thereafter the semiconductordevice 1 and the semiconductor chip 75 are mounted on this MCMsubstrate, and electrodes 76 of the semiconductor chip 75 and connectingelectrodes 72 a are connected with each other through wires 77. Further,a sealing member 79 is formed by one-side molding to cover thesemiconductor device 1, semiconductor chip 75, connecting electrodes 72,72 a and wires 77, to complete module packaging (S106). Then, asemiconductor module 70 thus fabricated is tested (S107) and defectiveproducts are removed, while non-defective products are shipped.

In forming MCM (MCP: Multi-Chip Package), stacking semiconductor chipsis effective for the reduction in size of MCP. In case of stackingsemiconductor chips, it is advantageous to adopt a method a face-downpackaging method wherein an underlying chip is connected to a modulesubstrate through salient electrodes. This is because, in comparisonwith the case where an underlying chip is mounted face up and wirebonding is performed, there are less restrictions on the size of thesemiconductor chip and the layout of electrodes formed on the mainsurface of the semiconductor chip, thus affording a package form of ahigher degree of freedom.

As to the semiconductor chip to be face-down-packaged, it is effectiveto form salient electrodes on the basis of the package form according tothe present invention.

More particularly, if there is adopted a bare chip packaging methodwherein salient electrodes are formed directly on electrodes (bondingpads) formed on the main surface of the semiconductor chip to beface-down-packaged and the chip is connected onto a module substratethrough those salient electrodes, the spacing of the salient electrodesis restricted by the spacing of the electrodes formed on thesemiconductor chip and is apt to become narrow. Consequently, it isnecessary to provide a module substrate having such a high dimensionalaccuracy as permits formation of fine wiring lines, with a consequentrise in unit price of parts giving rise to the problem that the modulecost becomes very high.

In the case where a wafer level package product (WPP product: WaferProcess Package product) is adopted as the semiconductor chip to beface-down-packaged, the unit price required for the packaging processapplied to defective chips is added to the unit price of non-defectivechips, so that the resulting rise in unit price of parts also causes theproblem of increase of the module cost.

In contrast therewith, the semiconductor module according to the presentinvention is kept low in its cost and is advantageous in that whensemiconductor chips are stacked within a package, it is also possible toattain the reduction of wall thickness which is required of individualsemiconductor chips.

Although the present invention has been described above concretely byway of embodiments thereof, it goes without saying that the presentinvention is not limited to the above embodiments, but that variouschanges may be made within the scope not departing from the gist of theinvention.

The following is a brief description of effects obtained by typicalmodes of the invention disclosed herein.

-   (1) The wire bonding electrodes arranged along the peripheral edges    of a semiconductor chip can be made into area array bump electrodes    of a larger pitch than the pitch of the wire bonding electrodes with    use of a wiring tape substrate, so that electric characteristics can    be improved. Particularly, the inductance which is essential to    high-speed signal processing can be decreased to about 0.1 nH from    that in the wire bonding method which is 1 to 1.5 nH.-   (2) By making the wire bonding electrodes into area array bump    electrodes larger and wider in pitch than the wire bonding    electrodes, it is possible to enhance the connection reliability at    the time of packaging the semiconductor device.-   (3) Since the wiring tape substrate with area array bump electrodes    formed thereon is of the same size as the semiconductor chip and is    superimposed on the semiconductor chip in registration with the    chip, it is possible to attain the reduction in size of the    semiconductor device.-   (4) Since plural semiconductor chips of different types can be    mounted to one and same wiring tape substrate, it is possible to    attain an MCM structure of the semiconductor device.-   (5) Since external connecting electrodes are arranged in area array,    the electrode pitch on a packaging substrate for the semiconductor    device can also be made large and thus it is possible to use a    conventional inexpensive insulating substrate (organic substrate)    fabricated by the laminate method.-   (6) Further, the semiconductor device is of a real chip size and is    reduced in size and weight, thus permitting flip-chip packaging and    high-speed signal transmission. Consequently, its application to a    portable device or a communication device can be expected.-   (7) It is possible to provide a semiconductor device which has a    stress relaxing structure between bump electrodes arranged in a    lattice shape and a semiconductor chip, as well as a method of    manufacturing the same.-   (8) It is possible to provide a semiconductor module (multi-chip    module) which can attain high-speed signal processing, high    function, high-density packaging, and reduction of thickness and    weight.    Industrial Applicability

As set forth above, the semiconductor device according to the presentinvention is useful for controlling an electronic device and for memoryand is suitable particularly for the attainment of high-speed signalprocessing, high function, high-density packaging, and reduction ofthickness and weight.

1. A method of manufacturing a semiconductor device, comprising thesteps of: providing a semiconductor chip including a main surface, aplurality of semiconductor elements formed over the main surface, and aplurality of electrodes; providing a wiring substrate including aflexible filmy insulating base layer provided with a main surface and aback surface, a plurality of wiring lines formed over the main surfaceof the insulating base layer, and through holes formed in the insulatingbase layer; forming gold salient electrodes respectively over theelectrodes of the semiconductor chip; disposing the wiring substrateover the main surface of the semiconductor chip through an adhesiveinterposed between the back surface of the insulating base layer and themain surface of the semiconductor chip; thereafter, applying pressure tothe wiring substrate to bring the gold salient electrodes and the wiringlines into mutual contact in the interiors of the through holes, andapplying heat to the adhesive to let the adhesive cure; and forming aplurality of solder salient electrodes over the main surface of thewiring substrate in such a manner that the solder salient electrodes areconnected to the plural wiring lines, wherein the plural solder salientelectrodes are arranged in a lattice shape of plural rows and columns ata pitch larger than a minimum pitch of the electrodes of thesemiconductor chip, and wherein the solder salient electrodes arearranged over the main surface of the semiconductor chip through theadhesive and the insulating base layer.
 2. A method of manufacturing asemiconductor device according to claim 1, wherein the adhesive is athermosetting resin.
 3. A method of manufacturing a semiconductor deviceaccording to claim 1, wherein the elastic modulus of the gold salientelectrodes is higher than the elastic moduli of the insulating baselayer and the adhesive.